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CS51221 Enhanced Voltage Mode PWM Controller
The CS51221 fixed frequency feed forward voltage mode PWM controller contains all of the features necessary for basic voltage mode operation. This PWM controller has been optimized for high frequency primary side control operation. In addition, this device includes such features as: Soft Start, accurate duty cycle limit control, less than 50A startup current, over and under voltage protection, and bidirectional synchronization. The CS51221 is available in a 16 lead SO narrow surface mount package.
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16 1 SO-16 D SUFFIX CASE 751B
* * * * * * * * * * * * * * *
Features 1.0 MHz Frequency Capability Fixed Frequency Voltage Mode Operation, with Feed Forward Thermal Shutdown Undervoltage Lock-Out Accurate Programmable Max Duty Cycle Limit 1.0 A Sink/Source Gate Drive Programmable Pulse-By-Pulse Overcurrent Protection Leading Edge Current Sense Blanking 75 ns Shutdown Propagation Delay Programmable Soft Start Undervoltage Protection Overvoltage Protection with Programmable Hysteresis Bidirectional Synchronization 25 ns GATE Rise and Fall Time (1.0 nF Load) 3.3 V 3% Reference Voltage Output
PIN CONNECTIONS AND MARKING DIAGRAM
1 GATE ISENSE SYNC FF UV OV RTCT ISET CS51221 AWLYWW 16 VC PGND VCC VREF LGND SS COMP VFB
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS51221ED16 CS51221EDR16 Package SO-16 SO-16 Shipping 48 Units/Rail 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
February, 2001 - Rev. 5
Publication Order Number: CS51221/D
BAS21
100
VIN (36 V to 72 V) FZT688 22 F 18 V 160 k T3 100:1 24.3 k 510 k 10 k T1 4:1 10 4.3 k D11 BAS21 100 pF 680 pF D13 V33MLA1206A23 MBRB2545CT 0.1 F T2 2:5 1.0 F
51 k
11 V
10
VOUT (5.0 V/5.0 A)
0.22 F VC VREF COMP OV ISET 13 k 20.25 k 10 IRF634 SS ISENSE PGND 62 470 pF 0.1 F 5.1 k 10 LGND FF GATE 2200 pF VFB RTCT SYNC CS51221 UV VCC 100 F SGND
10 k
200
1.0 F
CS51221
Figure 1. Application Diagram, 36 V-72 V to 5.0 V/5.0 A Converter
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5.6 k 180 150 4700 pF MOC81025 1.0 k
2
330 pF
0.01 F
2.0 k 1.0 k TL431 2.0 k
CS51221
ABSOLUTE MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Lead Temperature Soldering: Storage Temperature Range, TS ESD (Human Body Model) 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1.) Value Internally Limited 230 peak -65 to +150 2.0 Unit - C C kV
ABSOLUTE MAXIMUM RATINGS
Pin Name Gate Drive Output Current Sense Input Timing Resistor/Capacitor Feed Forward Error Amp Output Feedback Voltage Sync Input Undervoltage Overvoltage Current Set Soft Start Logic Section Supply Power Section Supply Reference Voltage Power Ground Logic Ground Pin Symbol GATE ISENSE RTCT FF COMP VFB SYNC UV OV ISET SS VCC VC VREF PGND LGND VMAX 15 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 15 V 15 V 6.0 V N/A N/A VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V N/A N/A ISOURCE 1.0 A Peak, 200 mA DC 1.0 mA 1.0 mA 1.0 mA 10 mA 1.0 mA 10 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 10 mA 10 mA lnternally Limited 1.0 A Peak, 200 mA DC N/A ISINK 1.0 A Peak, 200 mA DC 1.0 mA 10 mA 25 mA 20 mA 1.0 mA 10 mA 1.0 mA 1.0 mA 1.0 mA 10 mA 50 mA 1.0 A Peak, 200 mA DC 10 mA N/A N/A
ELECTRICAL CHARACTERISTICS (-40C < TA < 85C; -40C < TJ < 125C; 3.0 V < VC < 15 V; 4.7 V < VCC < 15 V; RT = 12 k; CT = 390 pF; unless otherwise specified.)
Characteristic Start/Stop Voltages Start Threshold Stop Threshold Hysteresis ICC @ Startup Supply Current ICC Operating IC Operating IC Operating Reference Voltage Total Accuracy 0 mA < IREF < 2.0 mA 3.2 3.3 3.4 V 1.0 nF Load on GATE No Switching - - - - 9.5 12 2.0 14 18 4.0 mA mA mA Start-Stop VCC < UVL Start Threshold - - 4.4 3.2 400 - 4.6 3.8 850 38 4.7 4.1 1400 75 V V mV A Test Conditions Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS (continued) (-40C < TA < 85C; -40C < TJ < 125C; 3.0 V < VC < 15 V; 4.7 V < VCC < 15 V;
RT = 12 k; CT = 390 pF; unless otherwise specified.) Characteristic Reference Voltage (continued) Line Regulation Load Regulation Noise Voltage Op Life Shift Fault Voltage VREF(OK) Voltage VREF(OK) Hysteresis Current Limit Error Amp Reference Voltage VFB Input Current Open Loop Gain Unity Gain Bandwidth COMP Sink Current COMP Source Current COMP High Voltage COMP Low Voltage PSRR SS Clamp, VCOMP COMP Max Clamp Oscillator Frequency Accuracy Voltage Stability Temperature Stability Max Frequency Duty Cycle Peak Voltage Valley Clamp Voltage Valley Voltage Discharge Current Synchronization Input Threshold Output Pulse Width Output High Voltage Input Resistance SYNC to Drive Delay Output Drive Current 100 A Load - Time from SYNC to GATE Shutdown RSYNC = 1.0 - - 0.9 200 2.1 35 100 1.0 1.4 320 2.5 70 140 1.5 1.8 450 2.8 140 180 2.25 V ns V k ns mA Note 2. - Note 2. - - - -40C < TJ < 125C. Note 2. Note 2. - 260 - - 1.0 80 1.94 0.9 0.85 0.85 273 1.0 8.0 - 85 2.0 0.95 1.0 1.0 320 2.0 - - 90 2.06 1.0 1.15 1.15 kHz % % MHz % V V V mA VFB = COMP VFB = 1.2 V Note 2. Note 2. COMP = 1.4 V, VFB = 1.45 V COMP = 1.4 V, VFB = 1.15 V VFB = 1.15 V VFB = 1.45 V Freq = 120 Hz. Note 2. SS = 1.4 V, VFB = 0 V, ISET = 2.0 V Note 2. 1.234 - 60 1.5 3.0 1.0 2.8 75 60 1.3 1.7 1.263 1.3 - - 12 1.6 3.1 125 85 1.4 1.8 1.285 2.0 - - 32 2.0 3.4 300 - 1.5 1.9 V A dB MHz mA mA V mV dB V V 0 mA < IREF < 2.0 mA 10 Hz < F < 10 kHz. Note 2. T = 1000 Hrs. Note 2. - - - - - - - - - 2.8 2.9 30 2.0 6.0 6.0 50 4.0 2.95 3.05 100 40 20 15 - 20 3.1 3.2 150 100 mV mV V mV V V mV mA Test Conditions Min Typ Max Unit
2. Guaranteed by design, not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued) (-40C < TA < 85C; -40C < TJ < 125C; 3.0 V < VC < 15 V; 4.7 V < VCC < 15 V;
RT = 12 k; CT = 390 pF; unless otherwise specified.) Characteristic GATE Driver High Saturation Voltage Low Saturation Voltage High Voltage Clamp Output Current Output UVL Leakage Rise Time Fall Time Max Gate Voltage During UVL/Sleep Feed Forward (FF) Discharge Voltage Discharge Current FF to GATE Delay Overcurrent Protection Overcurrent Threshold ISENSE to GATE Delay External Voltage Monitors Overvoltage Threshold Overvoltage Hysteresis Current Undervoltage Threshold Undervoltage Hysteresis Soft Start (SS) Charge Current Discharge Current Charge Voltage Discharge Voltage Soft Start Clamp Offset Soft Start Fault Voltage Blanking Blanking Time SS Blanking Disable Threshold COMP Blanking Disable Threshold Thermal Shutdown Thermal Shutdown Thermal Hysteresis Note 3. Note 3. 125 5.0 150 10 180 15 C C VFB < 1.0 VFB < 1.0, SS > 3.0 V - 50 2.8 2.8 150 3.0 3.0 250 3.3 3.3 ns V V FF = 1.25 V OV = 2.15 V or LV = 0.85 V SS = 2.0 V SS = 2.0 V - - 40 4.0 2.8 0.25 1.15 - 50 5.0 3.0 0.3 1.25 0.1 70 7.0 3.4 0.35 1.35 0.2 A A V V V V OV Increasing OV = 2.15 V UV Increasing - 1.9 10 0.95 25 2.0 12.5 1.0 75 2.1 15 1.05 125 V A V mV ISET = 0.5 V, Ramp ISENSE - 0.475 50 0.5 90 0.525 125 V ns IFF = 2.0 mA FF = 1.0 V - - 2.0 50 0.3 16 75 0.7 30 125 V mA ns 1.0 nF Load. Note 3. GATE = 0 V 1.0 nF Load, VC = 20 V, 1.0 V < GATE < 9.0 V 1.0 nF Load, VC = 20 V, 9.0 V < GATE < 1.0 V IGATE = 500 A VC - GATE, VC = 10 V, ISOURCE = 200 mA GATE - PGND, ISINK = 200 mA - - - 11 - - - - 0.4 1.5 1.2 13.5 1.0 1.0 60 25 0.7 2.0 1.5 16 1.25 50 100 50 1.0 V V V A A ns ns V Test Conditions Min Typ Max Unit
3. Guaranteed by design, not 100% tested in production.
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PACKAGE PIN DESCRIPTION
PACKAGE PIN # SO-16 1 PIN SYMBOL GATE FUNCTION External power switch driver with 1.0 A peak capability. Rail to rail output occurs when the capacitive load is between 470 pF and 10 nF. Current sense comparator input. Bidirectional synchronization. Locks to highest frequency. PWM ramp. Undervoltage protection monitor. Overvoltage protection monitor. Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX. Voltage at this pin sets pulse-by-pulse overcurrent threshold. Feedback voltage input. Connected to the error amplifier inverting input. Error amplifier output. Charging external capacitor restricts error amplifier output voltage during the power up or fault conditions. Logic ground. 3.3 V reference voltage output. Decoupling capacitor can be selected from 0.01 F to 10 F. Logic supply voltage. Output power stage ground. Output power stage supply voltage.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ISENSE SYNC FF UV OV RTCT ISET VFB COMP SS LGND VREF VCC PGND VC
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VCC 3.3 V + - + - UV Lockout Start/Stop S SYNC RTCT 2.0 V to 1.0 V Trip Points VBG (1.263 V) + EAMP - 3.0 V - + Max Duty Cycle (Sat Sense) SS to 1.8 V Max + COMP - Soft Start Clamp + - PWM Comp ON LGND 50 A VREF Q G1 OSC 13.5 V GATE UVL ENABLE VREF = 3.3 V 3.1 V - + Low Sat Gate Driver VC VREF OK Thermal Shutdown 2.0 mA (maximum load current) VREF
G2
R
Q
PGND
VFB
FF
FF Discharge
VO Off G4 Latching Discharge + - 2.0 V SS 5.0 A OV
G3 OV Monitor Max SS Det ILIM (Sat Sense) 3.0 V - + UV Monitor - +
ISET DISABLE ISENSE 150 ns Blank
+ -
UV 1.0 V
Figure 2. Block Diagram
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APPLICATION INFORMATION THEORY OF OPERATION
Feed Forward Voltage Mode Control
of the volt-second clamp are presented in the Design Guidelines section.
VOUT
In conventional voltage mode control, the ramp signal has fixed rising and falling slope. The feedback signal is derived solely from the output voltage. Consequently, voltage mode control has inferior line regulation and audio susceptibility. Feed forward voltage mode control derives the ramp signal from the input line, as shown in Figure 3. Therefore, the ramp of the slope varies with the input voltage. At the start of each switch cycle, the capacitor connected to the FF pin is charged through a resistor connected to the input voltage. Meanwhile, the Gate output is turned on to drive an external power switching device. When the FF pin voltage reaches the error amplifier output VCOMP, the PWM comparator turns off the Gate, which in turn opens the external switch. Simultaneously, the FF capacitor is quickly discharged to 0.3 V. Overall, the dynamics of the duty cycle are controlled by both input and output voltages. As illustrated in Figure 4, with a fixed input voltage the output voltage is regulated solely by the error amplifier. For example, an elevated output voltage reduces VCOMP which in turn causes duty cycle to decrease. However, if the input voltage varies, the slope of the ramp signal will react immediately which provides a much improved line transient response. As an example shown in Figure 5, when the input voltage goes up, the rising edge of the ramp signal increases which reduces duty cycle to counteract the change.
VIN Power Stage GATE Latch & Driver Feedback Network PWM FF COMP - + C Error Amplifier + - FB VOUT
VCOMP
FF VIN RTCT
GATE
Figure 4. Pulse Width Modulated by Output Current with Constant Input Voltage
VIN
VCOMP
FF IOUT RTCT
R
GATE
Figure 5. Pulse Width Modulated by Input Voltage with Constant Output Current
Powering the IC & UVL
Figure 3. Feed Forward Voltage Mode Control
The feed forward feature can also be employed to provide a volt-second clamp, which limits the maximum product of input voltage and turn on time. This clamp is used in circuits, such as Forward and Flyback converter, to prevent the transformer from saturating. Calculations used in the design
The Under Voltage Lockout (UVL) comparator has two voltage references; the start and stop thresholds. During power-up, the UVL comparator disables VREF (which in-turn disables the entire IC) until the controller reaches its VCC start threshold. During power-down, the UVL comparator allows the controller to operate until the VCC stop threshold is reached. The CS51221 requires only 50 A during startup. The output stage is held at a low impedance state in lock out mode. During power up and fault conditions, the soft-start clamps the Comp pin voltage and limits the duty cycle. The power up transition tends to generate temporary duty cycles
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much greater than the steady state value due to the low output voltage. Consequently, excessive current stresses often take place in the system. Soft Start technique alleviates this problem by gradually releasing the clamp on the duty cycle to eliminate the in-rush current. The duration of the Soft Start can be programmed through a capacitance connected to the SS pin. The constant charging current to the SS pin is 50 A (typ). The VREF (ok) comparator monitors the 3.3 V VREF output and latches a fault condition if VREF falls below 3.1 V. The fault condition may also be triggered when the OV pin voltage rises above 2.0 V or the UV pin voltage falls below 1.0 V. The under-voltage comparator has a built-in hysteresis of 75 mV (typ). The hysteresis for the OV comparator is programmable through a resistor connected to the OV pin. When an OV condition is detected, the over-voltage hysteresis current of 12.5 A (typ) is sourced from the pin. In Figure 6, the fault condition is triggered by pulling the UV pin to the ground. Immediately, the SS capacitor is discharged with 5.0 A of current (typ) and the GATE output is disabled until the SS voltage reaches the discharge voltage of 0.3 V (typ). The IC starts the Soft Start transition again if the fault condition has recovered as shown in Figure 6. However, if the fault condition persists, the SS voltage will stay at 0.1 V until the removal of the fault condition. sets the threshold for maximum current. As shown in Figure 7, when the ISENSE pin voltage exceeds the ISET voltage, the current limit comparator will reset the GATE latch flip-flop to terminate the GATE pulse.
Figure 7. The GATE Output Is Terminated When the ISENSE Pin Voltage Reaches the Threshold Set By the ISET Pin. CH2: ISENSE Pin, CH4: ISET Pin, CH3: GATE Pin
The current sense signal is prone to leading edge spikes caused by the switching transition. A RC low-pass filter is usually applied to the current signals to avoid premature triggering. However, the low pass filter will inevitably change the shape of the current pulse and also add cost. The CS51221 uses leading edge blanking circuitry that blocks out the first 150 ns (typ) of each current pulse. This removes the leading edge spikes without altering the current waveform. The blanking is disabled during Soft Start and when the VCOMP is saturated high so that the minimum on-time of the controller does not have the additional blanking period. The max SS detect comparator keeps the blanking function disabled until SS charges fully. The output of the max Duty Cycle detector goes high when the error amplifier output gets saturated high, indicating that the output voltage has fallen well below its regulation point and the power supply may be under load stress.
Figure 6. The Fault Condition Is Triggered when the UV Pin Voltage Falls Below 1.0 V. The Soft Start Capacitor Is Discharged and the GATE Output Is Disabled. CH2: Envelop of GATE Output, CH3: SS Pin with 0.01 mF Capacitor, CH4: UV Pin Oscillator and Synchronization
Current Sense and Over Current Protection
The current can be monitored by the ISENSE pin to achieve pulse by pulse current limit. Various techniques, such as a using current sense resistor or current transformer, can be adopted to derive current signals. The voltage of the ISET pin
The switching frequency is programmable through a RC network connected to the RTCT Pin. As shown in Figure 8, when the RTCT pin reaches 2.0 V, the capacitor is discharged by a 1.0 mA current source and the Gate signal is disabled. When the RTCT pin decreases to 1.0 V, the Gate output is turned on and the discharge current is removed to let the RTCT pin ramp up. This begins a new switching cycle. The CT charging time over the switch period sets the maximum duty cycle clamp which is programmable through the RT value as shown in the Design Guidelines. At the beginning
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CS51221
of each switching cycle, the SYNC pin generates a 2.5 V, 320 nS (typ) pulse. This pulse can be utilized to synchronize other power supplies.
Figure 9. Operation with External Sync. CH2: SYNC Pin, CH3: GATE Pin, CH4: RTCT Pin
Figure 8. The SYNC Pin Generates a Sync Pulse at the Beginning of Each Switching Cycle. CH2: GATE Pin, CH3: RTCT, CH4: SYNC Pin
DESIGN GUIDELINES
Switch Frequency and Maximum Duty Cycle Calculations
An external pulse signal can feed to the bidirectional SYNC pin to synchronize the switch frequency. For reliable operation, the sync frequency should be approximately 20% higher than free running IC frequency. As show in Figure 9, when the SYNC pin is triggered by an incoming signal, the IC immediately discharges CT. The GATE signal is turned on once the RTCT pin reaches the valley voltage. Because of the steep falling edge, this valley voltage falls below the regular 1.0 V threshold. However, the RTCT pin voltage is then quickly raised by a clamp. When the RTCT pin reaches the 0.95 V (typ) Valley Clamp Voltage, the clamp is disconnected after a brief delay and CT is charged through RT.
Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal sets the Gate output to the low state, thus providing a user selectable maximum duty cycle clamp. Charge and discharge times are determined by following general formulas;
tC + RTCT ln (VREF * VVALLEY) (VREF * VPEAK)
(VREF * VPEAK * IdRT) td + RTCT ln (VREF * VVALLEY * IdRT)
where: tC = charging time; td = discharging time; VVALLEY = valley voltage of the oscillator; VPEAK = peak voltage of the oscillator. Substituting in typical values for the parameters in the above formulas, VREF = 3.3 V, VVALLEY = 1.0 V, VPEAK = 2.0 V, Id = 1.0 mA:
tC + 0.57RTCT 1.3 * 0.001RT td + RTCT ln 2.3 * 0.001RT D max + 0.57 0.57 ) In 1.3*0.001RT 2.3*0.001R
T
It is noticed from the equation that for the oscillator to function properly, RT has to be greater than 2.3 k.
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CS51221
800 700 600 Frequency (kHz) 500 400 300 200 100 0 0.0001 RT = 50 K 0.001 CT (F) 0.01 RT = 10 K Duty Cycle (%) RT = 5.0 K 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 1000 10000 RT () 100000 1000000
Figure 10. Typical Performance Characteristics, Oscillator Frequency vs. CT Select RC for Feed Forward Ramp
Figure 11. Typical Performance Characteristics, Oscillator Duty Cycle vs. RT R2 V + 1.27 * R1 ) R2 OUT
If the line voltage is much greater than the FF pin Peak Voltage, the charge current can be treated as a constant and is equal to VIN/R. Therefore, the volt-second value is determined by:
VIN TON + (VCOMP * VFF(d)) R C
where is the correction factor due to the existence of the FB pin input current Ier.
+ (Ri ) R1 R2)Ier
where: VCOMP = COMP pin voltage; VFF(d) = FF pin discharge voltage. As shown in the equation, the volt-second clamp is set by the VCOMP clamp voltage which is equal to 1.8 V. In Forward or Flyback circuits, the volt-second clamp value is designed to prevent transformers from saturation. In a buck or forward converter, volt-second is equal to
VIN V TON + OUT n TS
Ri = DC resistance between the FB pin and the voltage divider output. Ier = VFB input current, 1.3 A typical.
VOUT Ier
R1 FB
- COMP +
Ri
n = transformer turns ratio, which is a constant determined by the regulated output voltage, switching period and transformer turns ration (use 1.0 for buck converter). It is interesting to notice from the aforementioned two equations that during steady state, VCOMP doesn't change for input voltage variations. This intuitively explains why FF voltage mode control has superior line regulation and line transient response. Knowing the nominal value of VIN and TON, one can also select the value of RC to place VCOMP at the center of its dynamic range.
Select Feedback Voltage Divider
+ -
1.27
R2
Figure 12. The Design of Feedback Voltage Divider Has to Consider the Error Amplifier Input Current
Design Voltage Dividers for OV and UV Detection
As shown in Figure 12, the voltage divider output feeds to the FB pin, which connects to the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to a 1.27 V (typ) reference voltage. The FB pin has an input current which has to be considered for accurate DC outputs. The following equation can be used to calculate the R1 and R2 value
In Figure 13, the voltage divider uses three resistors in series to set OV and UV threshold seen from the input voltage. The values of the resistors can be calculated from the following three equations, where the third equation is derived from OV hysteresis requirement.
VIN(LOW) R2 ) R3 + 1.0 V R2 ) R3 ) R1
(A)
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CS51221
VIN(HIGH) 12.5 mA R3 + 2.0 V R2 ) R3 ) R1 (R1 ) R2) + VHYST
(B)
VIN(LOW). Otherwise, two voltage dividers have to be used to program OV and UV separately.
(C) R1 VIN R2 R3
where: VIN(LOW), VIN(HIGH) = input voltage OV and UV threshold; VHYST = OV hysteresis seen at VIN It is self-evident from equation A and B that to use this design, VIN(HIGH) has to be two times greater than
VUV
VOV
Figure 13. OV/UV Monitor Divider
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PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-16 28 115 Unit C/W C/W
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Notes
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Notes
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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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CS51221/D

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